1.Field of the Invention
The present invention relates to a method for fabricating a fringe field switching (FFS) liquid crystal display (LCD) device and, more particularly, to a FFS LCD device which uses an organic insulating layer and consumes less power, and a method for fabricating the same.
2.Description of the Related Art
As the interest in information displays grows and demand for portable (mobile) information medium increases, research and commercialization of lighter and thinner flat panel displays (“FPD”) replacing conventional display devices such ascathode ray tubes (CRTs) have been actively ongoing. Among FPDs, the liquid crystal display (“LCD”) is a device for displaying images by using optical anisotropy of liquid crystal. LCD devices exhibit excellent resolution, color display and picture quality, so they are commonly used in notebook computers or desktop monitors, and the like.
The LCD includes a color filter substrate, an array substrate and a liquid crystal layer formed between the color filter substrate and the array substrate.
Here, a driving scheme generally used in the LCD includes a twisted nematic (TN) scheme in which liquid crystal molecules are driven in a direction perpendicular to a substrate, but the twisted nematic LCD device has shortcomings in that a viewing angle is as narrow as 90 degrees. This results from refractive anisotropy of liquid crystal molecules. Namely, when a voltage is applied to a panel, liquid crystal molecules, which are aligned to be horizontal to a substrate, is changed to be aligned to be substantially vertical to the substrate.
Thus, an in-plane switching (IPS) mode LCD device in which a viewing angle is improved to have 170 degrees or more by driving liquid crystal molecules in a direction horizontal to a substrate has been presented. An IPS mode LCD device will be described in detail as follows.
FIG. 1 is a schematic cross-sectional view illustrating a portion of an array substrate of an IPS mode LCD device. Specifically, FIG. 1 illustrates a portion of an array substrate of a fringe field switching (FFS) LCD device in which a fringe field formed between a pixel electrode and a common electrode drives liquid crystal molecules positioned on a pixel region and a common electrode through a slit to display an image.
In the FFS LCD device, in a state in which liquid crystal molecules are aligned horizontally, as a common electrode is formed in a lower side thereof and a pixel electrode is formed in an upper side thereof, electric fields are generated in horizontal and vertical directions, and thus, liquid crystal molecules are twisted and tilted to be driven.
As illustrated, in the general FFS LCD device, a gate line (not shown) and a data line 17 are arranged vertically and horizontally on a transparent array substrate 10 to define a pixel region, and a thin film transistor (TFT) as a switching element is formed in the intersection of the gate line and the data line.
The TFT includes a gate electrode 21 connected to the gate line, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to a pixel electrode 18. Also, the TFT includes a gate insulating layer 15a for insulating the gate electrode 21 and the source and drain electrodes 22 and 23, and an active layer 24 for forming a conductive channel between the source electrode 22 and the drain electrode 23 by a gate voltage supplied to the gate electrode 21.
Source and drain regions of the active layer 24 forms ohmic-contact with the source and drain electrodes 22 and 23 through an ohmic-contact layer 25n. 
The common electrode 8 and the pixel electrode 18 is formed in the pixel region, and the box-like shaped pixel electrode 18 includes a plurality of slits 18s therein in order to generate a fringe field together with the common electrode 8.
The pixel electrode 18 is electrically connected to the drain electrode 23 through a first contact hole formed in a first protective film 15b, a second protective film 15c, and a third protective film 15d. 
Meanwhile, a gate pad electrode 26p electrically connected to the gate line and the data line 17, respectively, is formed on the edge region of the array substrate 10 and delivers a scan signal and a data signal received from an external driving circuit unit (not shown) to the gate line and the data line 17.
Namely, the gate line and the data line 17 extend toward the driving circuit unit so as to be connected to the corresponding gate pad line 16p and the data pad line 17p, and the gate pad line 16p and the data pad line 17p receive a scan signal and a data signal from the driving circuit unit through the gate pad electrode 26p and the data pad electrode 27p electrically connected thereto, respectively.
The data pad line 17p is electrically connected to the data pad electrode 27p through a second contact hole, and the gate pad line 16p is electrically connected to the gate pad electrode 26p through a third contact hole.
The FFS LCD device configured as described above advantageously has a wide viewing angle, and in case the common electrode 8 is formed up to an upper portion of the data line 17, a black matrix region can be reduced to enhance an aperture ratio.
However, in case of forming an organic insulating layer with photo acryl to implement low power consumption, the upper third protective film 15d should be formed at a processing temperature lower than that of a previous process, namely, a photo acryl curing process. In this case, when a pad portion contact hole is formed, a problem that an undercut is formed within the pad portion contact hole arises. This will be described in detail with reference to the accompanying drawings.
FIG. 2 is a cross-sectional view schematically showing a portion of a pad portion of the general FFS LCD device illustrated in FIG. 1, in which a section of a gate pad portion in the course of forming a contact hole is illustrated.
Referring to FIG. 2, when the third protective film 15d is deposited at a low temperature, a bonding ratio of Si—N is so low as to have porous quality, and in this case, when the gate electrode layer 15a, the first protective film 15b, and the third protective film 15d are collectively dry-etched, the gate electrode layer 15a, the first protective film 15b, and the third protective film 15d are not uniformly etched due to a discontinuous deposition surface therebetween, generating an undercut within the pad portion contact hole H.
Thus, an interface between the gate insulating layer 15a and the first and third protective films 15b and 15d is reversely tapered to result in a defective contact between the gate pad electrode 26p and the gate pad line 16p, causing disconnection.
For reference, reference letters PR denote a photoresist pattern for forming the pad portion contact hole H.